This invention relates to the realization of a digital filter, in particular to the realization of a digital FIR filter of order N which comprises a modified digital filter of order 1 operating with a higher sampling rate. Further, the invention relates to a method to filter a M-times multiplexed input signal with such a digital FIR filter.
A digital filter of order 2N which receives a M-times multiplexed input signal which comprises a modified filter of order 1 in which 2N filter coefficients get periodically switched with a clock frequency that equals to M·2N-times the sampling rate of the input signal to set the filter periodically into M·2N internal filter states in each of which an internal output value is calculated before outputting one complete sample of the M-times multiplexed output signal is described in the European Patent Application EP 98 114 111.2 of the Applicant which content is herewith incorporated into this specification.
A special cost effective realization of such a filter is described in the Applicant's European Patent Application “Memory and Gate Effect Realization of a Digital Filter” which content is herewith incorporated into this specification.
These both documents show digital filters, preferably IIR filters, which have a clock frequency that equals to the sampling rate·number of multiplexes·filter order. Therefore, depending on the input signal and the wanted filter order it might be necessary to operate the respective filter with a comparatively high clock rate which results in a high needed processing power on the chip on which the filter is realized.
Therefore, it is the object underlying the present invention to provide an enhanced digital filter and method to filter a M-times multiplex input signal with a digital filter which require a reduced calculation power.